1. Field of the Invention
The invention relates in general to a system for processing a netlist description of a circuit to generate and display a schematic diagram, and in particular to a system that performs net routing on demand as a user zooms and pans the schematic diagram display.
2. Description of Related Art
An integrated circuit (IC) design engineer typically produces an IC design in the form of a gate level netlist indicating the various components (“cell instances”) to be included in the IC and indicating how their terminals are to be interconnected through nets. The designer can provide a netlist model of an IC as part of a test bench input to a computer-based circuit simulator to determine how the IC described by the netlist will behave, or as input to a placement and routing tool to determine where to place each cell instance within an IC layout and how to route the nets interconnecting the cell instances.
While a netlist makes a suitable input to a circuit simulator or placement and routing tool, it is not always easy for a human to comprehend how signals flow within a circuit by looking only at a text-based netlist model of the circuit. A schematic diagram provides a graphical view of a circuit, using graphical symbols to represent various types of cell instances and lines to represent nets interconnecting the cell instances making in easier for a designer to visualize the nature of the cell instances forming a circuit, the manner in which they are interconnected through nets, and the manner in which signals propagate through the circuit. A designer can employ a computer-aided schematic diagram generator to convert a netlist model of an IC into a schematic diagram model and to display it on a video monitor.
A typical schematic diagram generation system tries to produce a schematic diagram that makes it as easy as possible to trace the flow of information through the circuit it depicts. For example a typical schematic diagram generator tries to position representations of cell instances within a schematic diagram so that each cell instance is to the right of cell instances providing its input signals, and in a way that tries to minimize the number of intersections between nets and the number of jogs within each net interconnecting the cell instances. After positioning the cell instances, a typical schematic diagram generator then determines how to route nets between the cell instances in a way that avoids net overlap and provides sufficient separation between nets to avoid “visual crosstalk” when the schematic diagram is displayed at some minimum resolution. After determining a position for each cell instance representation and a route for each net, the system generates a display of the schematic diagram.
Display monitors normally do not have sufficient size or resolution to display the entire schematic diagram of a large circuit in a way that representations of cell instances and nets are clearly distinguishable. But a user can command a display system to zoom into some smaller portion of the schematic diagram, to display that portion of the schematic diagram with higher resolution, thereby allowing the user to clearly distinguish representations of all cell instances and nets in that area of the schematic. The user may also pan the display to show other areas of the schematic diagram with similar resolution.
One difficulty with prior art schematic diagram generators has been that they often take too long to produce a schematic diagram display for a large IC design. For example one conventional schematic diagram generator required about 6 hours to generate and display a schematic diagram for an IC having about 1.1 million cell instances.
One way prior art schematic diagram generators reduce the time required to generate a schematic diagram has been to reduce the complexity of the placement and routing algorithms employed by allowing the algorithms to violate some of criteria for the schematic diagram, for example by allowing excessive numbers of crossovers and jogs in the lines representing nets. But this can degrade the quality of the schematic diagram by making it more difficult for a user to trace signal paths through the circuit. Another way to reduce schematic diagram generation time is to partition the circuit design into separate sub-designs and to generate a separate schematic diagram display for each sub-design. But this “paginated” approach to schematic diagram generation fails to provide a full schematic diagram for the circuit and makes it difficult for a designer to trace signal flows over the entire design by preventing the designer from being able to smoothly pan the schematic diagram.
What is needed is a system for generating and displaying a full, un-paginated schematic diagram with less apparent delay.